Design, Fabrication, Characterisation and Simulation of Silicon p+np BBD Diodes
Papadopoulou, P., 2002, DUTh. doi: 10.12681/eadd/17427
Abstract: Bulk- Barrier Diodes (BBDs) are two - terminal three-layer structures similar to Bipolar Junction Transistors (BJT’s) of p+-n-p or n+-p-n type structures. However, contrary to the BJT’s, the middle (base) region in BBDs is so thin that it is normally fully depleted from free carriers, and also there exist no neutral region even for zero bias conditions (thermal equilibrium). As a result, a potential barrier is located inside the semiconductor. This potential barrier controls exponentially the current through the device. The potential barrier height can be controlled by well controllable technological parameters, such as dopant concentration and middle layer width, as well as by the applied bias voltage. This advantage and the fact that Bulk Barrier Diodes are majority carrier devices make them very attractive in many applications such as in high-speed applications or as photodiodes with high internal gain. So far, there are several published works, dealing with some very interesting applications of ΒΒD’s, based on the initially presented theoretical models such as the model of the dc electrical behavior or the theoretical model of the optoelectronic behavior. Although most experimental results can be well explained by the above models, these models do not include the effects of all technological parameters as well as the effects of applied bias conditions. Furthermore, no analytical model has been presented, that could describe one of the most important applications of ΒΒD, which is its application as high speed switching device (switching behavior). The present work attempts to give solution to the above problems, using the device simulation as the basic tool. Thus, it attempts to extend and complete the previous presented theoretical models with new analytical expressions of all the important quantities that describe the behavior of these structures, to investigate the validation limits of the new proposed models, as well as to optimize the performance of these devices in the different application areas.